1. Field of the Invention
The present invention relates to a method for monitoring fabrication parameters; especially, the present invention relates to a method for monitoring fabrication parameters applicable in semiconductor manufacturing.
2. Description of Related Art
In semiconductor manufacturing, each lot of wafers needs to pass through various fabrication processes so as to complete and form the required semiconductor components, wherein each process may influence the final yield and throughput of the semiconductor components.
Since every step performed within a process may involve several tools, suppose an engineer is informed of an abnormality in one lot of wafers (e.g. incorrect electrical features), it is actually very difficult to precisely locate the tool causing such an error among them. Additionally, because each tool has various fabrication parameters, it is even more challenging to further find out which fabrication parameter(s) is/are to be fixed.
It is possible to decide whether or not a certain fabrication parameters are responsible for a detected wafer abnormality by means of monitoring such fabrication parameters on every tool. However, this approach may not be precise; or sometimes the fabrication parameters have exceeded the limits, and so the tools alarmed and notified the engineer for verifications, but later it is realized that these fabrication parameters are not the actual causes for the wafer abnormality. And more seriously, duration required for verification by engineers may result in undesirable loss of tool throughput.
Furthermore, the fact that fabrication parameters did not exceed limits may not necessarily indicate that such fabrication parameters are not the real causes of the wafer abnormality. As the fabrication parameters fluctuate dramatically, wafer abnormality could be accordingly generated, but conventional solutions are incapable of distinguishing variations in fabrication parameters.
Therefore, how to effectively and quickly determine and locate the fabrication parameters leading to the wafer abnormality is indeed an issue that needs to be addressed for semiconductor manufacturers.
Accordingly, in consideration of the improvable drawbacks as discussed above, the inventors of the present invention propose a solution characterized in reasonable design and enabling effective improvement on the aforementioned defects.